Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO&#39;s

ABSTRACT

A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO&#39;s. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

TECHNICAL FIELD

Embodiments of the invention relate generally to an encoding process andmore particularly to a method and apparatus to generate Gray code forany even count value to enable efficient pointer exchange mechanisms inasynchronous First In First Out (FIFO) buffers.

BACKGROUND

In hardware devices requiring data transfer between multiple clockdomains, First In First Out (FIFO) buffers are often used to store andretrieve data. This is accomplished by writing the incoming data fromone clock domain in the FIFO and then retrieving the data from the otherclock domain. In addition to the data transfer across the clock domainboundary, write and read pointers of the FIFO are communicated acrossthese domains to flag FIFO full and empty conditions, as well as otherconditions.

A common problem in sending signals across clock domain boundaries ismetastability. Metastability exists when a signal is transitioningbetween states at the same time it is being sampled. The sampling deviceexpects one of either two states and is not configured to correctlyinterpret the transitioning signal. Metastability is always a designconcern in asynchronous environments.

To minimize metastability and other error conditions, the FIFO writepointer and read pointer is encoded in Gray code before transmission tothe other clock domain. This is done because of the adjacency principlebetween two successive Gray code values. This is true even when thepointer wraps around, i.e. while going from 7 (Gray code 100) to 0 (Graycode 000) there is only 1 bit change.

The benefits of Gray code counting techniques have long been recognized.Gray code can be described as an encoding of numbers resulting in anytwo adjacent numbers only differing by one digit. Ascending ordescending through a Gray code sequence of numbers results in exactlyone digit change, by either adding a new digit or by changing only oneexisting digit. This is beneficial in computing environments becauseadditional changes introduce opportunity for additional errors.

For example, the first four values of ordinary binary representation are00, 01, 10, 11. The change from the second number, 01, to the thirdnumber, 10, results in 2 digit changes. The 1's placeholder goes from 1to 0, and the 2's placeholder goes from 0 to 1. These types of changes,as stated above, provide opportunity for error introduction inelectromagnetic signaling systems.

The first four values of Gray code representation are 00, 01, 11, and10. As can be seen in this representation, exactly one digit changeexists for each adjacent Gray code representation. This is commonlycalled the adjacency principle. For any counting sequence, Gray coderepresentation therefore substantially decreases opportunity for errorintroduction.

One disadvantage to the Gray code counting technique is that it onlyworks when counting a number of values that is a power of 2, e.g. 2values, 4 values, 8 values, 16 values, etc. For instance, if the samecode was used to count 6 values (from 0 to 5), the moment the pointerwrapped around from 5 (111) to 0 (000), there would be a 3 bit change.Therefore, the adjacency principle of Gray code is currently onlyutilized when the range is a power of 2. This is a common problem in allFIFO's whose depth is not a power of 2.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example, and notnecessarily by way of limitation in the figures of the accompanyingdrawings in which like reference numerals refer to similar elements.

FIG. 1 is an illustration of one embodiment of a circuit for generatingGray code for any even count value to enable efficient pointer exchangemechanisms in asynchronous FIFO's.

FIG. 2 is an illustration of one embodiment of a circuit for conductinga bit-by-bit exclusive OR (XOR) as shown as the functional block labeledbit-by-bit XOR of the embodiment circuit in FIG. 1.

FIG. 3 is a flowchart illustrating one embodiment of a method forgenerating Gray code for any even count value to enable efficientpointer exchange mechanisms in asynchronous FIFO's.

FIG. 4 is an illustration of one embodiment of a computing systemcapable of generating Gray code for any even count value to enableefficient pointer exchange mechanisms in asynchronous FIFO's.

DETAILED DESCRIPTION

A method and apparatus for generating Gray code for any even count valueand, more particularly, to a method and apparatus to generate Gray codefor any even count value that, for example, may be applied to enableefficient pointer exchange mechanisms in asynchronous First In First Out(FIFO) buffers are disclosed. In this regard, an innovative Gray codegenerator is introduced to enable the adjacency principles and benefitsof Gray code to extend beyond even powers of two, for example if used topass pointers for a FIFO buffer of an even but non power of two depth.

In the following description numerous specific details are set forth inorder to provide a thorough understanding of embodiments of theinvention. It will be apparent, however, to one having ordinary skill inthe art that the specific detail need not be employed to practiceembodiments of the invention. In other instances, well known materialsor methods have not been described in detail in order to avoid obscuringthe present invention.

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the invention. The appearances of the phrase “in one embodiment” invarious places in the specification do not necessarily all refer to thesame embodiment.

As was shown above, the benefits of Gray code counting techniques havelong been recognized but have only limited application. The utility ofthe Gray code adjacency principle can be greatly expanded utilizingembodiments of the present invention. What is needed therefore is amethod and apparatus to utilize the adjacency principle of Gray code fora range of numbers that is not a power of two, in addition to the powerof two numbers for which it is currently used.

One embodiment provides a circuit design that results in an increasedapplication of Gray code. The embodiment provides an increased range,which includes the previous integer power of two values, including aswell all other even count values to result in a range of numbers thatwhen converted to Gray code representation result in the adjacencyprinciple applying not only between every value but also between thehighest and lowest value.

In FIG. 1, an embodiment of the present invention is disclosed incircuitry 100. It will be understood by one of ordinary skill in the artthat the circuitry as shown is for descriptive purposes only, and thatother variations for accomplishing the described aspects of thecircuitry may be employed without departing from the principles of orexceeding the scope of the present invention. Specifically, the need forthe top elements of the circuit 100 in FIG. 1, including maximum count102, binary count 104, subtractor 108, adder 110, right shift by 1register 112, multiplexer (MUX) 124, right shift by 1 register 114 andbit-by-bit XOR 116, may be obviated by replacing them with a hard codedvalue equal to their output and before the circuit is created.

The binary count 104 is a predetermined value that is dependent uponarchitecture needs. For example, the circuit 100 is used for generatingpointer values for a FIFO buffer in an asynchronous environment, thebinary count value would be set to the depth of the FIFO buffer. Forinstance when the FIFO buffer was 10 registers deep, the binary countvalue would be fixed at 1010, i.e., the binary representation of 10. Inthe present usage, maximum count 104 is defined as the maximum valuethat can be represented by the number of digits in a binaryrepresentation of a value. If the binary count 104 value is 1010, asshown above, then the maximum count 104 value would be 1111, or decimal15.

In this embodiment, a binary count value 104 is input to a subtractor108. The maximum count 102 is also connected to the subtractor 108. Thesubtractor 108 subtracts the binary count 104 value from the maximumcount 102 and provides this output to an adder 110. In the above examplethis would result in a value of 1111 minus 1010 resulting in 0101, whichis equal to decimal 15-10, or 5.

The adder 110 adds the value from the subtractor to the value 1 andoutputs to a right shift by 1 register 112. To continue the example,this results in the addition of 5 and 1 to yield 6, or in binary 0110.The right shift by 1 register 112 effectively divides the value from theadder by 2 and provides its output value to a multiplexer 124. Theexample number in this instance would be shifted to the right one,resulting in 011, which is decimal 3. The multiplexer 124 has 1 otherdata input that is hard coded at 0.

The same initial binary count value provided in block 104 also undergoesa test to determine if it is a power of 2. Binary count value 104 isinput to a right shift by 1 register 114 and then into a bit-by-bit XORcircuit 116 before the result is the selector value for the multiplexer.The multiplexer 124 therefore will select the output of the right shiftby 1 register 112 if the selector value is 0 and the multiplexer 124will select 0 as its output if the selector value is 1. The examplenumber would result in the binary count 104, in this case 1010, or 10,to be shifted to the right by one digit, resulting in 101. Running 101though the bit-by-bit XOR circuit 116 results in 0 as the selectingvalue for the MUX 124. In this case, the selector output by thebit-by-bit XOR 116 would cause the MUX 124 to select the value 011 fromthe right shift by 1 register 112 instead of the set 0 value on itsother input line.

These two elements, right shift by 1 register 114 and bit-by-bit XORregister 116, of the embodiment in FIG. 1 are a way to provide a circuitto account for integer powers of two values that do not require anoffset value before conversion to Gray code in order to maintaincomplete adjacency principle operation.

The output of the MUX 124, the offset value, is also listed in FIG. 1 asthe value “I”. The portion of the example circuit 100 that generates the“I” value may also be determined in advance, and the “I” value may behard coded. For example, in embodiments such as FIFO buffers inasynchronous environments, the buffer depth will be known and will oftenbe static hardware, therefore the “I” offset value can be determined inadvance and be used as an input to the lower portion of the circuit 100of the embodiment in FIG. 1. Furthermore, the entire circuit may beimplemented in software, including ASICs, CMOS, etc., in which case thecircuit may represent a flow chart of the software implementing anembodiment. It will be understood by one of ordinary skill in the artthat other means for providing the offset value may be used withoutexceeding or departing from the scope of the present invention, such asequivalent circuits or as a hard coded value or even as a value that wascalculated at least in part using software.

In FIG. 1, on the lower portion of the embodiment circuit 100, the “I”offset value and a binary counter's 130 values are inputs to an adder132. The adder 132 outputs the result to a binary to Gray converter 134.The output from the binary to Gray converter is the shifted value thatprovides complete adjacency principle operation for any even count rangeof numbers. To continue the above example, the “I” offset is selected at3, or in binary 011, when the buffer depth is 10. The binary counter 130would then output a range of 10 values, from 0 to 9, or in binary from0000 to 1001. Each of these values is added to the “I” value, in thisexample binary 011, to result in a shifted binary set of numbers with arange of 10 values. The shifted values may be used in additionalprocessing, for example, in Synchronization logic 136 as pointers forFIFO buffers in an asynchronous environment.

In FIG. 2, an embodiment 200 of the bit-by-bit XOR 116 circuit portionof the embodiment in FIG. 1 is shown. A bit-by-bit XOR may beimplemented by connecting the parallel bus 202 to a series of XOR gates.The XOR gates are connected in a fashion where the left most two bitsfrom the parallel bus 202 are XORed first in Exclusive OR gate 206. Theresult of this Exclusive OR operation is XORed with the third leftmostbit from the parallel bus 202 in Exclusive OR gate 210. The result ofExclusive OR gate 210 is XORed with the fourth leftmost bit from theparallel bus 202 in Exclusive OR gate 214.

The bit-by-bit XOR may be implemented on any data width and need not berestricted to the 4 bit wide example of the embodiment 200 in FIG. 2.Greater or fewer XOR gates may be added or subtracted such that they aresufficient to XOR in the fashion shown above for the entire data setprovided by the parallel bus 202. It will be understood by one ofordinary skill in the art that the bit-by-bit XOR circuit 200 shown inFIG. 2 may be implemented using different types or arrangements of gateswithout departing from the scope of the present invention.

It will be understood by one of ordinary skill in the art would be tocreate other flowcharts illustrating how to implement other embodimentsof the present invention that enable use of the adjacency principle ofGray code over any even count range of values. Turning now to FIG. 3,the particular methods of the invention are described in terms ofcomputer software with reference to a flowchart 300. The methods to beperformed by a computer constitute computer programs made up ofcomputer-executable instructions.

Describing the methods by reference to a flow diagram enables oneskilled in the art to develop such programs including such instructionsto carry out the methods on suitably configured computers (i.e., theprocessor or processors of the computer executing the instructions fromcomputer-accessible media). The computer-executable instructions may bewritten in a computer programming language or may be embodied infirmware logic. If written in a programming language conforming to arecognized standard, such instructions can be executed on a variety ofhardware platforms and for interface to a variety of operating systemsor without an operating system.

FIG. 3 is a flow chart 300 illustrating one embodiment of a process forgenerating Gray code for non integer powers of 2 even numbers. At block300 circuit 100 receives a value. At block 302 circuit 100 determinesthe number of binary digits to represent the received value. At block304 the result of block 302 is compared to the maximum count 102 thatmay be represented by the number of binary digits of the received value,and a difference is determined. In block 306 circuit 100 divides thedifference from block 304 by 2, thus obtaining a quotient. In block 308,the quotient is added to each value in a range from 0 to the receivedvalue. In block 310, the circuit 100 converts the result of block 308 tocorresponding Gray code representation.

FIG. 4 is a block diagram of one embodiment 400 of a computer system.Referring to FIG. 4, one embodiment 400 may be a networking device, orother computing system that operates as a router, server or hub or anyother node in a computer network exchanging signals between any othernetwork elements. The computer system illustrated in FIG. 4 is intendedto represent a range of computer systems. Alternative computer systemscan include more, fewer and/or different components.

Computer system 400 includes bus 401 or other communication device tocommunicate or transmit information, and processor 402 coupled to bus401 to process information. Processor 402 may include semiconductingprocessors generally, ASICs, PLDs, FPGAs, DSPs, embedded processors,chipsets, or any other processing device. While computer system 400 isillustrated with a single processor, computer system 400 can includemultiple processors and/or co-processors. Computer system 400 furtherincludes random access memory (RAM) or other dynamic storage device 404(referred to as main memory), coupled to bus 401 to store informationand instructions to be executed by processor 402. Main memory 404 alsocan be used to store temporary variables or other intermediateinformation during execution of instructions by processor 402.

Computer system 400 also includes read only memory (ROM) and/or otherstatic storage device 406 coupled to bus 401 to store static informationand instructions for processor 402. Data storage device 407 is coupledto bus 401 to store information and instructions. Data storage device407 such as a magnetic disk or optical disc and corresponding drive canbe coupled to computer system 400.

Computer system 400 can also be coupled via bus 401 to display device421, such as a cathode ray tube (CRT) or liquid crystal display (LCD),to display information to a computer user. Alphanumeric input device422, including alphanumeric and other keys, is typically coupled to bus401 to communicate information and command selections to processor 402.Another type of user input device is cursor control 423, such as amouse, a trackball, or cursor direction keys to communicate directioninformation and command selections to processor 402 and to controlcursor movement on display 421. Computer system 400 further includesnetwork interface 430 to provide access to a network, such as a localarea network.

Instructions are provided to memory from a storage device, such asmagnetic disk, a read-only memory (ROM) integrated circuit, CD-ROM, DVD,via a remote connection (e.g., over a network via network interface 430)that is either wired or wireless, etc. In alternative embodiments,hard-wired circuitry can be used in place of or in combination withsoftware instructions to implement embodiments of the invention. Thus,the present invention is not limited to any specific combination ofhardware circuitry and software instructions.

The apparatus may be specially constructed for the required purposes, ormay comprise a general-purpose computer selectively activated orreconfigured by a computer program stored in a computer. Such a computerprogram may be stored in a machine-readable storage medium, such as, butnot limited to, any type of magnetic or other disk storage mediaincluding floppy disks, optical storage media, CD-ROMs, andmagnetic-optical disks, read-only memories (ROMs), random accessmemories (RAMs), EPROMs, EEPROMs, Flash memory, magnetic or opticalcards; electrical, optical, acoustical or other form of propagatedsignals (e.g., carrier waves, infrared signals, digital signals, etc.),or any type of media suitable for storing electronic instructions, andeach coupled to a computer system bus.

In one embodiment a storage medium 407 including executable content orinstructions 408 is connected to control logic in the processor 402 toselectively access and execute the content 408 to implement generationof Gray code values for any even count range of values, an exampleapplication being used as pointers for FIFO buffers in an asynchronousenvironment, such that the pointers maintain the adjacency principles ofGray code between all values included when wrapping from the highestvalue in the range to the lowest value. It will be understood by one ofordinary skill in the art how to configure a Gray code generationcircuit or program to implement the creation of this range of valuesthat benefit from the adjacency principle.

The foregoing detailed description and accompanying drawings are onlyillustrative and not restrictive. They have been provided primarily fora clear and comprehensive understanding of the present invention and nounnecessary limitations are to be understood therefrom. Numerousadditions, deletions, and modifications to the embodiments describedherein, as well as alternative arrangements, may be devised by thoseskilled in the art without departing from the spirit of the presentinvention and the scope of the appended claims.

1-20. (canceled)
 21. A computing appliance comprising: a storage mediumincluding executable content; a control logic, coupled with the storagemedium to selectively access and execute the content to generate Graycode for any even range of values.
 22. A computing system according toclaim 21, further comprising an input port, to receive pointers for aFIFO buffer from a network device in one clock domain.
 23. A computingappliance according to claim 22 further comprising an output port,coupled to a network device in a different clock domain, to send thepointers to the network device.
 24. A method of obtaining Gray coderepresentations of values comprising: obtaining an even range of valuescorresponding to a received value; calculating an offset in accordancewith the received value; applying the offset to each value in the range;and converting the offset values to their Gray code representations. 25.The method of claim 24, wherein obtaining the even range of valuescorresponding to a received value further comprises: determining anumber of binary digits that represent the received value wherein amaximum value of the range is a largest value that can be represented bythe number of binary digits and a minimum value of the range is asmallest value that can be represented by the number of binary digits.26. The method of claim 25, wherein calculating an offset in accordancewith the received value further comprises: determining a differencebetween the maximum value and the received value; halving the differenceand calculating a remainder, wherein the remainder is the offset. 27.The method of claim 24, wherein applying the offset to each value in therange further comprises: adding the offset to each value in the range.28. The method of claim 25, wherein the smallest value is zero.
 29. Amethod comprising: receiving any integer of a range of integers, therange having a minimum integer and a maximum integer, the total numericcount of integers from the minimum integer to the maximum integer beingan even, non-power-of-two number; and representing the integer in Graycode representation.
 30. A method according to claim 29, whereinrepresenting the integer in Gray code further comprises: determining anumber of binary digits required to represent the received integer;subtracting the received integer from a maximum value represented whenall the binary digits are one to result in a difference; dividing thedifference by two to result in a quotient; adding the quotient to eachnumeric count from the minimum integer to the received integer to resultin a series of sums; and converting each sum to a corresponding Graycode representation.
 31. A method according to claim 29, whereinconverting each sum to Gray code representation comprises performing aconversion with a binary-to-Gray converter circuit.
 32. A countercircuit to produce a count according to the adjacency principle of Graycode, comprising: a binary counter to provide a binary integer, thebinary integer selected from a range of numbers represented by a minimumnumber to a maximum number, the range being any even value; and logiccoupled with the binary counter to receive the binary integer andgenerate a representation of the binary integer according to theadjacency principle.
 33. A counter circuit according to claim 32,wherein the logic further comprises arithmetic logic to perform additionand division.
 34. A counter circuit according to claim 33, wherein thelogic further comprises a exclusive OR (XOR) coupled with the arithmeticlogic to bitwise XOR selective outputs of the arithmetic logic.
 35. Acounter circuit according to claim 32, wherein the logic furthercomprises a binary-to-Gray conversion circuit.